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Validation, Test and Performance Characterization of DDR Memory Subsystems

                                                                                                       Questions?  Contact us!

Mobile memory demands the following:  Low power, high density (small size) and high performance.  The two leading technologies are LPDDR3 and the new and upcoming LPDDR4.  See below for some of our investigations around these two technologies:

LPDDR3

From a technology perspective LPDDR3 is a tough one since the Address/Command and Control bus is clocked on both edges of the DDR system clock.  However it is a lower pin count and can fit into small packages.  We have found a few JEDEC protocol violations on some LPDDR3 memory controllers (they shall remain unnamed!).

Request a copy of the DDR Detective® Probe Manager with example LPDDR3 data.

LPDDR4

This technology does not have a 'double pumped' Address/Command and Control bus but does use more overhead with multi clock Address/Command/Control protocol.  The specification has been released and is supported by the DDR Detective.  A copy of the LPDDR4 specification is available here.  If you have LPDDR4 testing needs please contact us.

FuturePlus Systems was chosen to give the LPDDR4 Compliance and Validation presentation at the JEDEC IOT and Mobile forum in Shanghai China in March 2016.  See the presentation here.