Mobile memory demands the following: Low power, high density (small size) and high performance. The three leading technologies are LPDDR3, LPDDR4, and LPDDR5. See below for some of our investigations around these two technologies:
LPDDR3
From a technology perspective LPDDR3 is a tough one since the Address/Command and Control bus is clocked on both edges of the DDR system clock. However it is a lower pin count and can fit into small packages. We have found a few JEDEC protocol violations on some LPDDR3 memory controllers (they shall remain unnamed!).
Request a copy of the DDR Detective® Probe Manager with example LPDDR3 data.
LPDDR4
This technology does not have a 'double pumped' Address/Command and Control bus but does use more overhead with multi clock Address/Command/Control protocol. The specification has been released and is supported by the DDR Detective. A copy of the LPDDR4 specification is available here. If you have LPDDR4 testing needs please contact us.
FuturePlus Systems was chosen to give the LPDDR4 Compliance and Validation presentation at the JEDEC IOT and Mobile forum in Shanghai China in March 2016. See the presentation here.
LPDDR5
The latest technology on the market has built-in bit specific trigger set up ability across all Address/Command/Control commands and bus signals or LPDDR5 protocol violations. The DDR Detective automated setup calibrates to the target and bus speed in minutes. Please visit here for more specific information on LPDDR5. If you have LPDDR5 testing needs please contact us.