Listed below are the Compliance Timing and Protocol rules that the DDR Detective® looks for. To the best of our knowledge our list is the most comprehensive in the industry. Find something missing? Contact us!
These are derived from the JEDEC specification for DDR3, DDR4 and LPDDR3. Timing violations are all done on clock edge boundaries. Event violations involve ordering issues like closing a bank that was not open. Additional compliance tests that involve data valid eye size and setup and hold measurements need to be done with an Oscilloscope or a logic analyzer. More information on those will be posted soon.
Even 5 years ago it was very difficult and expensive to perform these tests. Now with automated software and tools like the DDR Detective engineers can perform this validation much quicker and more cost effectively.
What happens if memory subsystems do not perform this type of testing? They run the risk of data corruption in the DRAM. Even if a memory subsystem is protected by ECC it can miss data corruption problems. ECC is only a double bit detection and single bit correction. Even if the ECC does find it the detection and correction wastes power and performance. Much better to have vendors properly validate their systems.